VIP Ensures Thorough, Seamless Coverage-Driven Verification Flow Between Simulation, Emulation, Formal Verification
SAN JOSE, CALIF –– December 3, 2019 ––
WHO: SmartDVTM Technologies, the Proven and Trusted choice for Verification and Design Intellectual Property (IP)
WHAT: Will highlight new additions to its extensive and broad portfolio of VIP that support TileLink, the chip-scale interconnect standard, and the Verilator open-source hardware description language (HDL) simulator at the RISC-V Summit. It will offer demonstrations of its Smart ViPDebugTM, a visual protocol debugger that reduces debug time.
WHEN: Tuesday, December 10, from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m.
WHERE: San Jose Convention Center, San Jose, Calif. Attendees can schedule Smart ViPDebug demos or meetings to learn how SmartDV’s VIP ensures a thorough and seamless coverage-driven verification flow with no coverage gaps between simulation, emulation or formal verification at demo@smart-dv.com.