Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
EEWeb
May 24, 2021
While a working device that meets all functional specifications is a chip design project group’s No. 1 goal, many designers wake up covered in sweat worrying about a dead-on-arrival chip. No matter how much coverage or how many verification tools are employed, a bug or multiple bugs could slip through the net.
This high-pressure, demanding engineering environment requires three independent technology-based verification tools at the functional level to guarantee a bug-free functional and highly reliable chip. The overlap in verification and test coverage may seem to be excessive. Many sleep-deprived designers believe the additional effort is worthwhile.
The three functional-level verification steps –– functional verification, functional test, and built-in self-test (BIST) –– each offer a sense of confidence in the chip’s design. Combining them triples the sense of confidence that the chip will work as the functional spec intended.
Functional verification is the most resource-hungry step because it uses an abundance of available EDA tools and plenty of the hours budgeted for verification. Functional verification must encompass both functional coverage and code coverage. The two approach the verification problem differently and are necessary for ensuring comprehensive verification.
Functional coverage answers the question: Does the functional behavior of the design match the specifications for what the chip is supposed to do? Testing the behavior of the device against the specifications is necessary. Not enough, as the expected functional behavior reveals little about what happens when unanticipated states or inputs are encountered.
This is where code coverage looks at the design structure (code) rather than the design specification and can uncover behaviors not contemplated in the functional specification. For example, there may be states or inputs that are never expected to exist in normal operation. What happens if such an unexpected state or input does occur? How does the chip respond? It is possible that the chip will exhibit a behavior that was never anticipated.
By complementing each other, functional coverage and code coverage quantify functional verification and help to take the design to the next sequential steps of synthesis, tape-out, and eventually silicon. Functional verification that achieves both functional and code coverage closure flushes out most or all functional bugs of the design. Of course, the end goal is not the design but the chip that will be manufactured based on the design.
Once the chip has been manufactured, functional test and BIST are used to flush out any bugs that arise due to manufacturing defects or are caused by other issues during the manufacturing process. Depending on what is implemented per the design for test, planning with BIST determines any overlap in testing with functional test executed to make sure all manufactured transistors and wires are defect-free. A well-thought-out testing strategy that includes BIST can reduce time on the tester, lowering the time and cost of manufacturing test, and test critical internal areas of the chip that would be difficult to set up using external test approaches. A second key benefit of BIST is that it can be deployed for use at any time during the lifetime of the device, a necessary strategy for some applications.
Use of embedded FPGAs can simplify functional device testing because the FPGA is a pre-verified component guaranteed to behave as it was programmed, minimizing testing. While a BIST implementation in an FPGA brings in area and performance overhead, using it has substantial benefit, including better testing and the ability to test the device once it is installed in a system.
An encompassing verification strategy that pairs functional design verification with a comprehensive functional test strategy is needed to reduce the possibility of a dead-on-arrival device.