Contact Us
AVSBus Master
Design IP
Overview

AVSBus (Adaptive Voltage Scaling Bus) is commonly integrated into comprehensive power management systems within System-on-Chips (SoCs) to oversee voltage and frequency adjustments across various system elements, thereby guaranteeing the utmost power efficiency and performance. SmartDV offers a complete, scalable, and silicon-proven solution for AVSBus. SmartDV’s AVSBus Master design IP core is highly customizable to optimize design area, power, and performance for both ASIC and FPGA flows, providing flexibility to adapt to specific design requirements.

AVSBus Master
Benefits
  • Multiple back to back frames and status for higher bus efficiency
  • Supports 2-wire and 3-wire mode
  • Clock pausing between command frames
  • Bus timeout function
  • Slave status response frames
Compliance and Compatibility
  • AVSBus as defined in Part III of PMBus Specification 1.3.1
  • All major EDA synthesis, simulation, and linting flows