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AVSBus Slave
Design IP
Overview

SmartDV’s AVSBus Slave IP is a silicon-proven solution designed for efficient power management communication between digital controllers and voltage regulators in high-performance systems. Fully compliant with the PMBus and AVSBus specifications, it enables dynamic voltage scaling, reducing power consumption and improving overall system efficiency.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It supports seamless integration into SoC designs and ensures reliable communication with minimal latency, making it ideal for data center, networking, and enterprise-grade applications.

AVSBus Slave
Benefits
  • Multiple back to back frames and status for higher bus efficiency
  • Supports 2-wire and 3-wire mode
  • Slave pin zero interrupt
  • Clock resynchronization
  • Bus timeout function
Compliance and Compatibility
  • AVSBus as defined in Part III of PMBus Specification 1.3.1
  • All major EDA synthesis, simulation, and linting flows