SmartDV’s CXL 3.x Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring fabric-scale coherent memory connectivity, enhanced security, and multi-level switching in AI accelerator, HPC, and hyperscale data center applications. Fully compliant with CXL 3.2 and backward compatible with CXL 3.1, 3.0, 2.0, and 1.x, it delivers the complete CXL 3.x protocol stack on the PCIe 6.0 physical interface at 64 GT/s, with doubled bandwidth over CXL 2.0 and significant capabilities for fabric management, trusted execution environments, and advanced memory device management.
Designed for the extreme demands of hyperscale AI and data center chiplet architectures, the IP implements the complete CXL 3.x feature set including CXL.io, CXL.cache, and CXL.mem across all device types, fabric capabilities with multi-level switching, peer-to-peer DMA and memory sharing between accelerators, Trusted Security Protocol for trusted compute environments, enhanced memory expander functionality, CXL 1.1/2.0/3.x Control and Status Registers, up to 4K payload size and 256 functions, CXL Error VDM Format, buried cache state rules, QoS Telemetry for memory, Advanced Error Reporting, data poisoning, all snoop responses, and Hot/Warm/Cold Reset support.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of advanced process nodes.
