Contact Us
MIPI ASPMI Slave
Design IP
Overview

SmartDV’s silicon proven MIPI ASPMI Slave interface provides full support for the two-wire MIPI ASPMI synchronous serial interface, compatible with the ASPMI Specification. Through its SPMI slave compatibility, it provides a simple interface to a wide range of low-cost devices. This design IP is highly customizable to optimize design footprint and performance for both ASIC and FPGA flows.

Request Data Sheet
MIPI ASPMI Slave
Benefits
  • The following device interrupts are supported:
    • Edge sensitive interrupts
    • Level sensitive interrupts
    • Group interrupts
    • SPS (system power state) interrupts
    • DVC group interrupts
    • LDO and DVC interrupts
    • Buck DVC interrupts
    • Interrupt priority queuing
    • IRQH enable register (disabling of IRQ generation functionality based on NACK retry limit)
    • Generation of group event on any internal SPMI error logged in an ERROR CTRL register
  • Supports virtual wires on SPMI (supports both scheme 1 and scheme 2)
  • Short addressing modes
  • Control on Register0 write and power mode command (sleep/wakeup/shutdown/reset) reception
  • Slave-to-slave (STS) transmit and receive command filtering
  • SGPIO functionality
  • Ability to generate an empty arbitration request
Compliance and Compatibility
  • ASPMI Specification 1.7
  • MIPI SPMI Specification 1.0
  • MIPI SPMI Specification 2.0
  • Full MIPI SPMI slave functionality
  • ACK/NACK (per 2.0 Spec)

Request Datasheet