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MIPI ASPMI Slave
Design IP
Overview

SmartDV’s MIPI ASPMI Slave IP is a silicon-proven solution designed to streamline power management communication between system components in mobile and embedded devices. It ensures reliable, low-latency control of power modes and voltage scaling, in compliance with ASPMI specifications.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Ideal for power-sensitive applications, the IP enables seamless integration into complex SoCs, facilitating efficient power sequencing and system-level power control.

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MIPI ASPMI Slave
Benefits
  • The following device interrupts are supported:
    • Edge sensitive interrupts
    • Level sensitive interrupts
    • Group interrupts
    • SPS (system power state) interrupts
    • DVC group interrupts
    • LDO and DVC interrupts
    • Buck DVC interrupts
    • Interrupt priority queuing
    • IRQH enable register (disabling of IRQ generation functionality based on NACK retry limit)
    • Generation of group event on any internal SPMI error logged in an ERROR CTRL register
  • Supports virtual wires on SPMI (supports both scheme 1 and scheme 2)
  • Short addressing modes
  • Control on Register0 write and power mode command (sleep/wakeup/shutdown/reset) reception
  • Slave-to-slave (STS) transmit and receive command filtering
  • SGPIO functionality
  • Ability to generate an empty arbitration request
Compliance and Compatibility
  • ASPMI Specification 1.7
  • MIPI SPMI Specification 1.0
  • MIPI SPMI Specification 2.0
  • Full MIPI SPMI slave functionality
  • ACK/NACK (per 2.0 Spec)

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