MIPI UniPro Controller

Design IP

Overview

MIPI UniPro is a high-performance serial interconnect bus for mobile and other applications. SmartDV offers a complete, silicon-proven solution for MIPI UFS and MIPI UniPro together with MIPI M-PHY. SmartDV’s MIPI UniPro controller design IP core is highly optimized for area, power, and performance, delivering 10Gbps per lane for HS-G4 and 20 Gbps per lane for HS-G5.

Benefits

CPort arbitration at segment and packet level with a maximum of 32 CPorts
Multiple M-PHY lanes for UFS
Advanced PHY layer feature integration for link, encoding, initialization and so on
Various power mode support: MIPI UniPro power management modes
All data-link layer, network layer, transport layer features, and DME features
End-to-end flow control and error handling
L1.5 PHY testing

Compliance and Compatibility

MIPI UniPro Specification 1.6/1.8/2.0
MIPI M-PHY Specification 3.0/4.0/4.1/5.0
MIPI UFS Specification 2.1/3.0/3.1/4.0
All major EDA synthesis, simulation, and linting flows