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VESA DSC Decoder
Design IP
Overview

SmartDV’s VESA DSC (Display Stream Compression) Decoder IP is a silicon-proven, high-efficiency solution designed to support visually lossless video compression in high-resolution display systems. Compliant with the VESA DSC specification, it enables reduced bandwidth and power consumption without compromising image quality, making it ideal for applications such as mobile devices, automotive displays, and 8K televisions.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance.

VESA DSC Decoder
Benefits
  • Input buffering compatible with transport streams over video interfaces such as HDMI 2.1, MIPI DSI, and DisplayPort
  • Support for 3 pixels per clock per slice
  • Support for 1/2/4/8/16 slices per line
Compliance and Compatibility
  • DSC Specification 1.1/1.2a
  • Compatible with DisplayPort
  • Compatible with HDMI
  • Compatible with MIPI DSI
  • All major EDA synthesis, simulation, and linting flows