Is it possible to make a design change and not have to rerun the entire regression suite?
By Brian Bailey, Semiconductor Engineering
April 28, 2022
Verification consumes more time and resources than design, and yet little headway is being made to optimize it.
The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences?
In the design flow, tools and methodologies have been created to minimize the chance of problems, particularly as you approach tape-out, by making safe, non-optimal corrections. But there are no such tools or methodologies for verification.
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And they can be more complete. “In simulation, it may be hard to cover the entire state space of inputs and study their impacts on the outputs to get 100% coverage for verification,” says Bipul Talukdar, director of application engineering for SmartDV. “Formal verification can help exercise the entire state space and quickly produce counter-examples for changed behaviors. The key to the formal verification approach is to encode the changed behaviors in properties.”