Will Feature Portfolio of SmartDV Verification IP, Demonstrate Smart ViPDebug Protocol Debugger
SAN JOSE, CALIF. –– November 6, 2019 –– SmartDVTM Technologies will exhibit at SemIsrael Expo 2019 in Airport City, Israel, November 19 and ICCAD China 2019 November 21-22 in Nanjing, China.
At both events, SmartDV will showcase why it is the Proven and Trusted choice for Verification and Design Intellectual Property (IP), including new additions to its extensive and broad portfolio of protocols. SmartDV’s latest VIP supports the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system-on-chip (SoC) designs, and Verilator, the free, open-source hardware description language (HDL) simulator.
In addition, SmartDV will demonstrate its Smart ViPDebugTM, a visual protocol debugger that reduces debug time by rapidly identifying violations.
SemIsrael and ICCAD China attendees can schedule meetings to discuss SmartDV’s Verification and Design IP or arrange for private demos of Smart ViPDebug at demo@smart-dv.com.