Will Present “Design Successes with Verification IP” as part of the ES Design West “Meet the Experts” Program
SAN JOSE, CALIF –– June 27, 2019 ––
WHO: SmartDVTM Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation emulation, field programmable gate array (FPGA), formal models and post-silicon validation platforms, Design IP and rapid customized VIP and Design IP development
WHAT: Will demonstrate Smart ViPDebugTM, a protocol debugger that rapidly identifies violations through linked waveform and transaction database views to reduce debug time in booth #2226 at ES Design West, a co-located event at SEMICON West. Highlighted will be SmartDV’s comprehensive portfolio of VIP compatible with all verification languages, platforms and methodologies, Design IP, SimXLTM portfolio of Synthesizable Transactors, assertion IP and post-silicon VIP. Featured VIP will be its new OpenCAPI, Compute Express Link (CXL), Ethernet Time-Sensitive Networking (TSN) and TileLink interconnect standards.
WHEN: Tuesday through Thursday, July 9-11. ES Design West attendees can schedule demonstrations through: demo@smart-dv.com
WHERE: Moscone Center South Hall in San Francisco
Bipul Talukdar, SmartDV’s director of Applications Engineering North America, will present “Design Successes with Verification IP” as part of the ES Design West “Meet the Experts” Advanced Applications session Thursday, July 11, at 3:10pm. It will be held at the SMART Design Pavilion.