Deepak Kumar Tala, CEO, SmartDV
EEWeb
April 10, 2019
Chip design teams employ Verification IP to improve quality, reduce the risk of silicon re-spins, accelerate project delivery, and increase ROI.
Verification engineers have it tough these days. They have the critical, but often thankless, task of verifying the functional correctness of complex SoC designs filled with integrated blocks of IP, many of which are based on complicated industry-standard interface protocols.
The lengthy verification process that they endure is comprised of, at a minimum, simulation- or hardware-emulation–based techniques that use a framework or testbench with stimulus generators, scoreboards/checkers, and functional coverage models.
Even so, functional bugs continue to evade them, and these functional bugs are the major cause of costly silicon re-spins. Verification completeness has never seemed harder or more elusive.
Some relief comes in the form of libraries of reusable verification components and pre-defined functional blocks called Verification IP (VIP) that create an infrastructure to support industry-standard interfaces and accelerate verification sign-off. Verification IP completes the verification environment to ensure that debug, coverage closure, and quality are improved and that project schedules are reduced. Better yet, Verification IP provides the verification team with a known reference against which the design under verification can be compared.
Typically, Verification IP is supplied as industry-standard, compliant, plug-and-play modules using different hardware verification languages (HVLs) — notably the universal verification methodology (UVM), SystemVerilog, and SystemC. Verification IP, it should be noted, is not another verification methodology, such as UVM for building testbenches, but is a key component of the verification methodology.
Verification IP is used to verify system-level functionality and validate target performance by generating application-specific traffic. A testbench for a complex SoC is complicated and requires a variety of Verification IPs to generate comprehensive tests and stimulate and verify different interfaces and standard bus protocols. Verification IP should include transactions/sequences, drivers, configuration components, a test plan for a specific interface, and test suites to connect to a design under test (DUT) inside the testbench to simulate or emulate an IP block or a complete SoC design.
Frequently, Verification IP is provided by third-party vendors with domain expertise who often are active participants in interface standards development organizations for networking, storage, automotive, bus, MIPI, display protocols, and others. In many cases, they have distinct advantages and unique capabilities unmatched by in-house resources. These third parties are noted for verifying the correct functionality and compliance with the industry standard of the production-proven core that they provide through a full test suite of functional coverage models. Each Verification IP block for emulation and FFGA-based prototyping comes as synthesizable register transfer level (RTL) code and full application programming interface (API) compatibility to seamlessly move designs from simulation to emulation. These vendors have experience from working with other users on previous tape-outs and know how to detect hard-to-find design bugs. Some boast of more intelligent debuggers, faster compile and system-level simulation run times, and fast firmware/software development. Most offer a variety of support options and customization to meet the verification engineering group’s needs.
With verification consuming approximately 70% of a project’s schedule, Verification IP has become an essential piece of today’s verification strategy. Chip design verification groups employ it in the verification environment to improve quality, reduce the risk of silicon re-spins, accelerate project delivery, and increase return on investment (ROI).